Pin grid array (PGA) packages are well known in the art. During flip chip attach of a microelectronic die to a substrate including a PGA thereon, a reflow process typically occurs at high temperatures, such as, for example, at about 230 degrees Celsius to join solder bumps on the PGA substrate to conductive bumps, typically Cu bumps, on the die. The reflow process softens and melts not only the solder bumps on the PGA substrate, but also the solder, such as SnSb (sometimes alloyed with Au from the substrate lands), that is typically used to attach the pins of the PGA to lands on the package substrate (hereinafter “pin-attach solder”). In addition to a softening of the pin-attach solder reflow of the solder bumps on the PGA substrate volatile material trapped in the pin-attach solder tends to vaporize and, along with any air voids trapped in the pin-attach solder, try to escape from the same. A softening of the pin-attach solder and movement of the vaporized volatile material and air voids therein during reflow contribute to lift and pin and cause a tilting of the pins supported by the pin-attach solder. The above problem is exacerbated as pins are getting smaller and therefore lighter, and as pin count/pin density increases.
The above problem is exacerbated by the use of lead free C4 solder metallurgy and NiPdAu surface finishing. Specifically speaking, the increase of the melting point of lead-free SnAg solder over eutectic SnPb requires the peak temperature of a typical die attachment process to be about 230 degrees Celsius, which overlaps the melting range of the pin attach solder SnSb. As a result, a softening of the SnPb occurs, which may result in up to about 20% pin tilt failure of assembled packages. A second aspect of the problem is that, as compared with a pairing of SnSb with ENIG, SnSb displays poorer wetting interaction with NiPdAu, which may result in more solder voiding entrapment under the pins. Limited x-sectional observation shows about 30% of pins in such a situation as having voids greater than 200 microns. The presence of such large voids can also result in mechanically weak PGA joints as well as in pin movement.
FIG. 1 shows a PGA joint formed according to the prior art. In FIG. 1, a side view is shown of one of a pin 1 in a tilted state after C4 bumping. The pin 1 is shown as being mounted onto substrate 5. Pin 1 includes a pin stem 2 and a pin head 4 attached to the pin stem. The pin head 4 is shown as being mounted onto a land pad 8 on a PCB-side surface 6 of substrate 5 using a pin-attach solder joint 10 as shown. As seen in FIG. 1, the pin-attach solder joint 10 includes voids therein which have tilted the pin 1 for the reasons explained above, thus weakening the electrical and mechanical bond between pin 1 and land pad 8.
The prior art attempts to address the problem of pin tilt include reducing the reflow temperature in order to control a softening of the pin-attach solder and a movement of vaporized volatile material therein. Doing so has shown to improve pin tilt yields, but, disadvantageously, requires very accurate control of the C4 die attach process, even during high volume manufacturing, and further increases the risk for non wets/de-wets on the die to substrate interconnection. The above method may cause insufficient solder joint strength and more void entrapment during C4 die attach simply because a lower peak temperature can jeopardize the processing window for C4 attachment.
The prior art fails to provide an effective method of minimizing pin tilt during flip chip attach of a die to a PGA substrate.
For simplicity and clarity of illustration, elements in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Where considered appropriate, reference numerals have been repeated among the drawings to indicate corresponding or analogous elements.